As integrated circuit feature size has decreased a method of sidewall image transfer (SIT) patterning has been employed for advanced integrated circuit manufacture. However, when used to fabricate the electrical interconnects of the wiring levels, wires formed at one wiring level using SIT cannot be connected to wires formed by non-SIT patterning on the same level and another wiring level must be used to do so. This adds integrated circuit design restrictions which complicates, or in some cases excludes, certain circuit features from the integrated circuit design. Accordingly, there exists a need in the art to eliminate the deficiencies and limitations described hereinabove.